Video card integration: Part 2

About a year ago I gave some thought on how to have such a graphics chip render ASCII bytes in memory into characters on the screen, storing the typeface in ROM, to reduce the memory footprint on the CPU.

I know it would be difficult to utilize, but could the ram that would have been accessed during the blanking time on each scan line (I believe it is 33 bytes per line) be used to store data? It would be a complicated memory map. I am wondering if it could be used to store some type of program data

Great video, very educational and exciting! I like how you went through the troubleshooting of the random pixels and didn't just wire it up so it would look correct the first time.

I think you can avoid the front of line noise by taking the CPU off the bus using the inverted sync pulse signal instead of the active area signal? This should get the CPU off the bus in time for the first pixel in each line since it’d now effectively be synchronizing on the back porch and there are more than 10 pixels (i.e. more than one CPU clock cycle) from there to the start of the active area.

(Ugh this comment box code is such garbage...submitted before I was ready!) I'm also glad we didn't have to "sacrifice" use of the small LCD to add this video card to an existing setup. I'll probably tidy up the interconnection between the two boards with a quicker single ribbon cable connection so the main can be used with or without on a whim.

It will be interesting to see the blanking interval CPU perf diff between 1mhz and 4mhz. I clocked my mainboard to 4mhz a while back. Made the tiny games I've been writing buttery smooth and results in better looking graphic update times on the little LCD.

This video was all I was hoping it would be. One curiosity...why do you have the power filter capacitors on the computer breadboard but not on the video card breadboard? Is this because the cpu is only sensitive to the power fluctuations and the simple logic chips on the video card are not?

I was waiting for this video since a long time.. feels amazing..!

It's great to see this coming together, and seeing some familiar problems and some new ones! One thing to be careful of that you didn't mention is the RDY pin. If the CPU hits a WAI instruction (intentionally or not) it will drive RDY low, so my understanding is that you ought to always connect it through a resistor rather than driving it directly.

I was wondering if that CPU was updating the full frame buffer only a couple of times per second, thus giving a small march to the left, OR is it updating the full framebuffer just under 64 times per frame, so that MOST of the frames back to back are the same, but slowly the CPU and video card "slip" in their timings which gives us the slow march to the left. My back of the napkin math indicates the first situation is true, given that there's 6.4k of memory allocated to the video card (100 pixels x 64 pixels at one byte per pixel) and 1 MHz * 0.3 / 60 frames/second gives us only about 5,000 clock cycles per second. Each instruction is going to take multiple clock cycles, and it takes quite a few instructions to update each pixel. I'm amazed that it runs as fast as it does, actually! Instead of sharing memory access between the video card and the CPU, how difficult would this idea be: You have a RAM chip in low memory dedicated to the CPU that only the CPU can access, you have the ROM in high memory that only the CPU can access, and you have some address space blocked off in middle memory somewhere. That middle RAM actually gets connected to two different RAM chips, switched by buffers. When the buffers are in one state, middle RAM chip A is connected only to the CPU, and middle RAM chip B is connected only to the video card. Then the CPU can run at full speed doing whatever it needs to. Every vertical blanking interval at a certain scan line, the video card triggers an interrupt on the CPU. The CPU can then decide if it's ready to "flip" the buffers, and if so, change the configuration on the buffers to make middle RAM B connect to CPU, and middle RAM A connect to Video card. This scheme would get you like, 99% of full speed for the CPU, eliminate the noise you have on the left side of the screen, allow for full page updates without seeing the CPU draw out the image, and make this fast enough to potentially run DOOM, which let's face it, we ALL want to see it run DOOM now.

Great work Ben! One question, just for my understanding: at https://youtu.be/IwgUPQH1H_o?t=715 you state that it's ok for the '245 to read at any time, but won't it put random data from the data bus into VGA in the last CPU clock cycle before the CPU gets disabled? Doesn't it make more sense to hook the latch output up to the transceiver as well? I'm no expert in any sense so maybe I'm just confused.

Looks great - really enjoyed the problem-solving

The best part: My graphics card is on the way and will be here latest Monday! :-) Two comments: In the end at 42:35 you say "we only get 70% efficiency because the CPU is halted 70% of the time" That would make it 30% efficiency, or? Also starting at 14:57 you add two control signals that are not neatly bent and square, but they go right up to the buffers. I was so sure the reason was that you would replace them in the course of the video in the process of bugfixing, but you never did. Why did you not make those two cables neat and square? Were you running out of yellow wire? I assume there will be a part 3 where you fix the last display errors and write a more interesting program? I can't wait, I absolutely love those videos!

Great video, but I am a bit disappointed that you stray from your normal very tidy breadboard wiring with the chip enable wires on the graphics card. It seems very atypical to all of your other videos.

Watching this one allowed me to finally understand why in computers like the old Commodores you could increase the processing by introducing blank lines between every other line. Another amazing video, Ben! What about a collab with the 8-Bit Guy? I really think that you could do something really cool

Ive been waiting for this and im so excited!