RAM and bus timing — 6502 part 6
So here's part 6 of the 6502 series. As you can see from the comments and edit I made to the previous post, I decided to split this into two videos, the first of which is here.
That means part 7 will basically be everything after 33:00 in the previous post's video. I plan to make part 7 public in about 2 weeks to keep the public releases spaced more evenly.
I plan to flip this video public in the morning, so if you notice any big goofs, please let me know! I made a lot of changes at the last minute, so hopefully all is well.
Comments (7)
I’m using ~RD for OE on both the EPROM and the SRAM on my Z80 project. It works well because the ~RD only becomes active when the addresses are stable. I’m using ~WR (write) for the SRAM, and the same is true for the timing, the address and data bus are both stable at ~WR. Of course, the Z80 has separate ~RD and ~WR signal lines, so memory is easy to interface. I loved the timing tutorial, it was a great logical look at the timing signals, and I did review the Z80 timing as a good refresher. I’m running at 2.5MHz, so have a shorter timing for SRAM, and had to have a close look at it’s timing diagrams. But I think it is OK for this project.
I have been studying that 65C02 timing diagram for over a year now, for my VIC20 @ 8mhz project (my first of this scale), and I bumped into the same ambiguities. I knew 90% already, the other 10% really cleared up some things for me. Great in-depth explanation!
Those timing diagrams are terrifying... I'm in the planning stages of my own retro PC (z80 based) and honestly didn't know how I was gonna get through verifying the timings and everything. This video has given me I think a good primer into how to understand those diagrams, but of course the proof will be in the doing it myself when the time comes. :3 Thanks Ben ^.^
Thanks for this video and the whole series. One super quick question about the tADS and the tAH values: in the video you seem to use the 14MHz values from the RAM data sheet; 30ns for tADS and 10ns for tAH. But would it not be the case that tADS would be significantly higher when running @1Mhz (@2Mhz the datasheet says 150ns, so presumably ~300ns)? That would eat a fair way into the 500ns clock pulse switch, or am I missing something? Not enough to throw off the timing for the read/writes, but the 30 on the diagram was eating me up through the video :/
The way I read it, the different columns are based on the voltage the chip is run at. So it's not that the times get longer if you run the clock slower; the times get longer if you run at a lower voltage, and because the times get longer, the clock must get slower. In other words, at 1.8 volts, tADS is max 150ns, but the clock cycle time, tCYC, is a min of 500ns, so the clock can only run at 2Mhz. But at 5 volts, tADS is max 30ns and tCYC is min of 70ns, so the clock *can* run up to 14Mhz, but it doesn't have to go that fast because tCYC is only a minimum. Hopefully that makes sense
Thanks Ben... things are always better the 2 nd time i look at them... like the inclusion about propagation delays on the logic gates.... off to do some scoping around and see this timing in action....
No big goofs, but maybe add a quick comment about why we care about RAM timing but didn't worry when hooking the EPROM up?